Wires notify gates, and an agenda turns delay into simulated time.
Build mutable wires, delayed gate actions, an ordered agenda, and a half-adder whose output changes only after the scheduled propagation delay.
Guiding question
How can local gate rules combine into a circuit whose behavior unfolds through explicit simulated time?
Store one signal and action list inside each wire
Run wire actions only when a signal actually changes
Schedule gate updates at current time plus a fixed delay
Propagate agenda events in nondecreasing simulated time
Compose primitive gates into a half-adder without central circuit logic
A wire owns a signal and a list of action procedures. Installing a gate adds an action to each input wire and runs it once so the initial output is scheduled. Later, set-signal! calls those actions only when the signal changes. Each gate reads its current inputs immediately but schedules the output mutation for a later agenda time.
The half-adder is built from or, and, inverter, and another and gate. The finite schedule first settles the zero inputs, then changes a, b, and a again. The recorded times are exact simulation events derived from the explicit delays in this model.
Separate immediate input reads from delayed output mutations. Follow sorted agenda insertion, each current-time update, and the wire actions triggered by a changed signal. In the half-adder, identify which primitive gate schedules every transition in sum and carry.
Try it yourself
Change the program and compare the result.
Add a second half-adder and an or gate to build a full-adder. Drive three finite input combinations, record simulated times, and explain which output transitions share a time but arise from different scheduled events.
Show hint
A full-adder combines two half-adders and ORs their carry outputs. Keep all delays explicit rather than computing the truth table centrally.